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NTE1167 Integrated Circuit Phase Lock Loop (PLL) Frequency Synthesizer
Description: The NTE1167 consists of a crystal oscillator, 10 bit divider, phase comparator, and a programmable divide-by-N 9-bit counter in a single CMOS 16-Lead DIP type integrated circuit. This device is designed for use in frequency synthesizers and phase locked loop applications for CB transceivers since it includes a reference frequency selector pin. Absolute Maximum Ratings: (TA = +25C unless otherwise specified) Supply Voltage, VDD - VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS VIN VDD Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250mW Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30 to +70C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125C Lead Temperature (During Soldering, 5sec Max), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260C Electrical Characteristics: (VDD - VSS = 6V, -30 TA +70C, fin Qin = 10.24MHz unless otherwise specified)
Parameter Input Voltage (All Inputs) Low Level High Level Pull-Up Resistance Pull-Down Resistance Supply Current Output Voltage High Level Low Level Output Current High Level Low Level Output Voltage Symbol VIL VIH RUP FS RDN P0 - P8 IDD VOH LD VOL LD ISAT H DO ISAT L DO VIF Fin VIF FS VIF P0 - P8 Max Input Frequency Max Free Running Frequency Operating Voltage fIN Max Qin fIN Max Fin fFR Max FIN VDD VDD = 5.5V, Vin Fin = 1VP-P, Exclude sink current of preset pin IOH = 0.1mA IOL = 0.1mA VO = 0V VO = 0V VDD = 5V Note 1 Test Conditions Min - 5.5 - 15 - Typ Max Unit - - 2.0 75 5.0 0.5 - 0 - 9.0 V V M k mA
5.5 0 400 400 1.7 5.5 - 11 3.3 3.5 5.0
- - - - 2.2 - - - - - -
- 0.5 - - 2.8 - 0.5 - - - 6.5
V V A A V V V MHz MHz MHz V
Note 1. All inputs refers to pins P0 to P8, FS, Fin, and Qin. This parameter defins their input levels at DC coupling.
Pin Connection Diagram
VDD PIN RIN N.C. DO LD P8 P7
1 2 3 4 5 6 7 8
16 VSS 15 P0 14 P1 13 P2 12 P3 11 P4 10 P5 9 P6
16
9
.260 (6.6) Max
1
8
.785 (19.9) Max .200 (5.08) Max .245 (6.22) Min
.300 (7.62)
.100 (2.54) .700 (17.7)

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